Study of Electrical Engineering. In my diploma thesis I explored tightly coupled FPGA architectures for instruction set extensions of a 32-bit microprocessor.
| Description | |||
|---|---|---|---|
| 2017 | Present | | Working at TU Dresden as a research assistant, refer to my Google Scholar profile. |
| 2017 | Present | | Working part time at Racyics as an R&D engineer for IP development and design services, including projects with Infineon, Renesas, Globalfoundries, and Hyperstone. |
| 2011 | 2017 | | Study of Electrical Engineering. In my diploma thesis I explored tightly coupled FPGA architectures for instruction set extensions of a 32-bit microprocessor. |
| Skill | Proficiency |
|---|---|
| RTL design (mainly SystemVerilog, some VHDL) | |
| Verification, including UVM | |
| Integration of various 3rd party IPs | |
| Synthesis and timing constraints | |
| DFT concepts and architecture | |
| Lab bringup and test pattern development | |
| Bare metal software for Arm and RISC-V CPUs | |
| Prompting AI agents for hardware designs |
| Tapeout | Node | Description | Contribution | Reference |
|---|---|---|---|---|
| 2025 | 22 nm FD-SOI | 1024-ch brain interface | Support in architecture, STA debugging, FPGA concept for lab eval | |
| 2025 | 16 nm FinFET | Edge AI chip for video processing | Toplevel design and integration of VLIW DSP core | |
| 2025 | 12 nm FinFET | Automotive MCU | Toplevel design and IP integration | |
| 2024 | 22 nm FD-SOI | IP Testchip | Toplevel design, netlist verification | |
| 2022 | 22 nm FD-SOI | ADC Testchip | IP integration | |
| 2022 | 22 nm FD-SOI | IP Testchip | Toplevel design, netlist verification | |
| 2021 | 22 nm FD-SOI | Ethernet Testchip with RISC-V core | RISC-V CPU integration, verification, lab eval | ISOCC |
| 2020 | 22 nm FD-SOI | IP Testchip with multiple Arm CPU and library variants | CPU integration, verification, test pattern development and extensive yield evaluation | |
| 2020 | 22 nm FD-SOI | RISC-V core with Ethernet PHY and an OPC UA engine | Toplevel design, verification, lab eval | TVLSI |
| 2019 | 22 nm FD-SOI | IP Testchip | Arm CPU integration, netlist verification, lab eval | ESSDERC |
| 2019 | 130 nm SiGe | 60 GHz Radar | IP integration and verification | heise.de IEEE |
| 2019 | 22 nm FD-SOI | IP Testchip | Arm CPU integration, netlist verification | TCAS |
| 2019 | 22 nm FD-SOI | ADC Testchip | RISC-V CPU integration, verification, lab bringup | BioCAS |
| 2019 | 22 nm FD-SOI | IP Testchip | Toplevel design and Arm CPU integration, lab eval | Cool Chips |
| 2018 | SATA Flash controller | Netlist verification, MBIST integration | ||
| 2016 | 28 nm | internal test chip with proprietary 32-bit CPU and BTLE | RTL design of CPU and integration |